1. Introduction
This invention relates to electroplating non-conductors. More particularly, this invention relates to improved compositions for electroplating the surface of a non-conductor using a preformed colloid of a metal sulfide. The metal sulfide functions as a base for direct electroplating. The invention is especially useful for the manufacture of printed circuit boards.
2. Description of the Prior Art
Nonconducting surfaces are conventionally metallized by a sequence of steps comprising catalysis of the surface of the nonconductor to render the same catalytic to electroless metal deposition followed by contact of the catalyzed surface with an electroless plating solution that deposits metal over the catalyzed surface in the absence of an external source of electricity. Metal plating continues for a time sufficient to form a metal deposit of the desired thickness. Following electroless metal deposition, the metal deposit is optionally enhanced by electrodeposition of a metal over the electroless metal coating. Electrolytic deposition is possible because the electroless metal deposit serves as a conductive base coating that permits electroplating.
Catalyst compositions useful for electroless metal plating are known in the art and disclosed in numerous publications including U.S. Pat. No. 3,011,920 incorporated herein by reference. The catalyst of this patent consists of an aqueous suspension of a tin-noble or precious (catalytic) metal colloid. Surfaces treated with such catalysts promote the generation of electrolessly formed metal deposits by the oxidation of a reducing agent in an electroless plating solution catalyzed by the catalytic colloid.
Electroless metal plating solutions are aqueous solutions containing both dissolved metal ions and a reducing agent in solution. The presence of both the dissolved metal ions and the reducing agent in solution results in plate-out of metal when in contact with a catalytic metal-tin catalyst. However, the presence of the dissolved metal and reducing agent in solution may also result in solution instability and indiscriminate deposition of metal on containers walls for the plating solution. This may necessitate interruption of the plating operation, removal of the plating solution from its container and cleaning of the walls and bottoms of the containing with an etching solution. Indiscriminate deposition may be avoided by careful control of the plating solution during use by addition of stabilizers to the solution which inhibit indiscriminate deposition, but which also retard plating rate.
Attempts have been made in the past to avoid the use of an electroless plating solution by a direct plating process whereby a metal is deposited directly over a treated nonconducting surface. One such process is disclosed in U.S. Pat. No. 3,099,608, incorporated herein by reference. The process disclosed in this patent involves treatment of the nonconducting surface with a tin-palladium colloid which forms an essentially non-conducting film of colloidal palladium particles over the nonconducting surface. This is the same tin-palladium colloid used as a plating catalyst for electroless metal deposition. For reasons not fully understood, it is possible to electroplate directly over the catalyzed surface of the nonconductor from an electroplating solution though deposition occurs by propagation and growth from a conductive surface, such as the copper cladding used in the fabrication of a printed circuit board. Therefore, deposition begins at the interface of an adjacent conductive surface and the catalyzed nonconducting surface. The deposit grows epitaxially along the catalyzed surface from this interface. Metal deposition onto the substrate using this process is slow. Moreover, deposit thickness is uneven with the thickest deposit occurring at the interface with the conducting surface and the thinnest deposit occurring at a point most remote from the interface.
It is stated that an improvement to the process of U.S. Pat. No. 3,099,608 is described in UK Patent No 2,123,036 B, incorporated herein by reference. In accordance with the process described in this patent, a surface is provided with metallic sites and the surface is then electroplated from an electroplating solution containing an additive said to inhibit deposition of metal on a metal deposit formed during the plating reaction without inhibiting deposition on the metallic sites over the nonconducting surface. This is said to result in preferential deposition over the metallic sites with a concomitant increase in the overall plating rate. In accordance with the patent, the metallic sites are preferably formed in the same manner as in the aforesaid U.S. Pat. No. 3,099,608 --i.e., by immersion of the nonconducting surface in a solution of a tin palladium colloid. The additive in the electroplating solution responsible for inhibiting deposition is described as one selected from a group of dyes, surfactants, chelating agents, brighteners and leveling agents. Many of such materials are conventional additives in electroplating solutions.
There are limitations to the above process. Both the processes of the US and UK patents require conductive surfaces adjacent to the nonconducting surface for initiation and propagation of the electroplated metal deposit. For this reason, the processes are limited in their application to metal plating solutions of nonconducting substrates in areas in close proximity to a conductive surface.
One commercial application of the process of the UK patent is for the metallization of through-holes walls in the manufacture of double sided printed circuit boards by a process known in the art as panel plating. In this application, the starting material is a printed circuit board substrate clad on both of its surfaces with copper. Holes are drilled through the printed circuit substrate at desired locations. For conductivity, the hole walls are catalyzed with a tin-palladium colloid to form the required metal sites on the walls of the through-holes. Since the circuit board material is clad on both of its surfaces with copper and the circuit board base material is of limited thickness, the copper cladding on the surfaces of the circuit board material is separated by the thin cross section of the substrate material. The next step in the process is direct electroplating over the catalyzed hole walls. Since the copper cladding on each surface is separated by the relatively small thickness of the cross section of the substrate, during electroplating, deposition initiates at the interfaces of the copper cladding and the through-hole walls and rapidly propagates into the holes. The hole wall is plated to a desired thickness within a reasonable period of time. Thereafter, the circuit board is finished by imaging and etching operations.
A disadvantage to the above panel plating process is that copper is electroplated over the hole walls and over the entire surface of the copper cladding. The steps following plating involve imaging with an organic coating to form a circuit pattern and removal of copper by etching. Therefore, copper is first electrolytically deposited and then removed by etching, a sequence of steps which is wasteful of plating metal, etchant and time, and therefore, expensive.
The art, recognizing the disadvantages of panel plating, developed a process for manufacturing printed circuit boards known as pattern plating. In this process, a printed circuit board base material is drilled at desired locations to form through-holes. Through-holes are metallized using conventional electroless plating techniques. Electroless copper is plated onto the walls of the through-holes and over the copper cladding. Thereafter, a photoresist coating is formed and imaged to form the circuit pattern. The board is then electroplated with copper depositing on the copper conductors and through-hole walls, but not over the entire surface of the copper cladding. Soldermask is then plated over the exposed copper by immersion plating or electroplating and the remaining photoresist is removed. The copper not protected by the solder is then removed by etching to form the copper circuit.
Pattern plating cannot be used with the metallizing process of the above referenced UK patent. Treatment of copper cladding prior to the application of the photoresist and the development of the photoresist, all as required for pattern plating, requires the use of treatment chemicals that dissolve or desorb tin-palladium colloid from the hole walls. Since removal occurs prior to electroplating, direct electroplating to provide conductive through-holes is impossible.
Further improvements in processes for direct electroplating of nonconductors are disclosed in U.S. Pat. Nos. 4,895,739; 4,919,768 and 4,952,286, each incorporated herein by reference. In accordance with the processes of these patents, an electroless plating catalyst, such as that disclosed in the UK patent, is treated with an aqueous solution of a chalcogen, such as a solution of a sulfur compound, to convert the catalytic surface to a chalcogenide surface. The chalcogenide of the electroless plating catalyst formed by conversion of the surface to a chalcogenide conversion coating is a robust coating. Therefore, plating catalyst is not desorbed from the nonconductive surface by pretreatment or metallization. Consequently, it is possible to pattern plate substrates for formation of printed circuit boards using the process of said patents.
The processes of the aforementioned patents provide a substantial improvement over the process of the UK patent. However, it has also been found that contact of an adsorbed catalytic metal with a chalcogen solution, especially a solution of a sulfur compound, results in formation of a chalcogenide layer on all metal surfaces in contact with the solution. Therefore, if the process is used in the manufacture of printed circuit boards, copper cladding on the printed circuit board base material is converted to a copper chalcogenide as is the catalytic metal. If the copper chalcogenide is not removed prior to plating, it will reduce bond strength between the copper and a metal subsequently deposited over the copper.
In addition to the above, the art of printed circuit board manufacture is moving in the direction of horizontal processing. Equipment for horizontal processing is more compact than equipment used for vertical processing and can accommodate fewer treatment solutions. For this reason, printed circuit board manufacturers are attempting to shorten the process line--i.e., reduce the number of processing steps and treatment solutions required for the manufacture of printed circuit boards.
A shortened process for electroplating using a chalcogenide is disclosed in U.S. Pat. No. 5,276,290 incorporated herein by reference. In accordance with the process disclosed in this patent, a stable colloid of a preformed catalytic chalcogenide is prepared. A non-conducting surface is contacted with the colloid by immersion. The colloidal chalcogenide adsorbs on the surface of the nonconductor. Following adsorption of the colloidal chalcogenide, the non-conductor is electroplated following procedures disclosed in the aforesaid U.S. Pat. Nos. 4,895,739; 4,919,768 and 4,952,286.
The process of U.S. Pat. No. 5,276,290 is an improvement over the earlier processes for plating non-conductors because there are fewer processing steps and metal surfaces do not come into contact with a solution of a chalcogen to form a chalcogenide requiring removal prior to plating. The process of this patent is illustrated by the following sequence for plating through-holes in printed circuit board manufacture and is compared to a conventional plating process requiring electroless metal deposition.
______________________________________ Conventional Process Patented Process ______________________________________ Step 1 Desmear with chromic or Step 1 Same; sulfonic acid or plasma; Step 2 clean and condition with Step 2 same; detergent type cleaner; Step 3 microetch copper Step 3 immerse in preformed cladding; solution of catalytic chalcogenide; Step 4 catalyst predip; Step 4 microetch copper cladding; Step 5 catalyze with catalytic Step 5 electroplate to full colloid; thickness; Step 6 deposit electroless metal; Step 7 electroplate to full thickness. ______________________________________
A reduced number of processing steps results from elimination of the need to separately treat the non-conductor with a colloidal catalytic solution followed by the solution of the chalcogen and by avoidance of an etch step to remove metal chalcogenide formed over metallic surfaces. Also, the process of U.S. Pat. No. 5,276,290 replaces the need for electroless plating with a direct electroplating step eliminating the need for a costly electroless metal plating solution and the associated problems of solution instability and disposal.
Though the process of U.S. Pat. No. 5,276,290 provides the advantages described above, in practice, it has been found that the colloid formed by the process disclosed in the patent, though adequately stable for use as a freshly prepared colloid, is inadequately stable for prolonged storage prior to use. This limits the market for the colloid. Moreover, it has been found that the quality of the metal deposit formed by electroplating using the preformed colloid varies in unpredictable manner. In particular, metal coverage over a surface treated with the preformed colloid and adhesion to the surface is found to vary from batch to batch of preformed colloid thereby further limiting the commercial use of the same.